Insulating layers are commonly used to separate conductors or semi-conductors in the manufacture of computer components. Such layers are used in the construction of both computer chips and packages for carrying the chips.
Most such insulating layers have holes or vias made in them. The walls of the vias are often plated with a conductor, such as copper, to provide electrical communication between conductive or semi-conductive materials on either side of the layer.
When straight walled vias are formed in the insulating layer by, e.g., drilling or directional plasma etching, a problem is often encountered with the integrity of the conductive material which is subsequently deposited on the via walls. The conductive material is sometimes observed to crack and then to peel or to flake away from the sharp corners where the straight walls of the vias meet the planar surface of the insulating layer.
Considerable effort has gone into efforts to overcome this problem. Sloped vias which avoid the sharp corners where the via walls meet the surface of the resinous layer have been generally accepted as a useful solution to the problem. However, an optimum method for making sloped vias in resinous layers, especially in the dry or plasma manufacturing of computer components has, until now, not been found.
U.S. Pat. No. 4,369,090 to Wilson et al describes a method of fabricating a cured polyamic acid film with sloped vias. The Wilson et al method includes the partial curing of a polyamic acid film at a certain critical chronostatic temperature prior to wet chemical etching of vias in order to achieve a controlled slope of the via wall. The desired tapering effect of Wilson et al is obtained due to the nature of the partial curing or imidization step.
U.S. Pat. No. 4,411,735 to Belani indicates that in the wet etching of vias the slope of the via wall can be controlled between 45 and 90 degrees by the selection of etchants.
U.S. Pat. No. 4,482,427 to Hiraoka describes a dry process for forming via holes with sloped walls in a polymer layer by oxygen reactive ion etching through a perforated mask. Hiraoka accomplishes the sloped vias by positioning the mask a critical distance above the polymer layer.
U.S. Pat. No. 4,487,652 to Almgren describes the transfer of the slope in the walls of a mask aperture to the walls of an underlying polyimide via by careful control of a plasma with respect to the predetermined etching selectivity of the mask material and the polyimide.
U.S. Pat. No. 4,495,220 to Wolf et al shows the use of a phosphorous doped silicon dioxide mask to form sloped vias in an underlying polyimide layer. Oxygen plasma etches polyimide exposed through openings in the silicon dioxide mask and also etches polyimide under the mask around the openings. Bowl shaped voids are formed in the polyimide under the openings and extending around the openings. The doped silicon dioxide mask is removed to expose the sloped vias.
U.S. Pat. No. 4,354,897 to Nakajima shows a method of forming a sloped via in an insulating layer which includes the step of wet chemical etching through a photoresist mask in such a way that the wet etching undercuts the photoresist mask, softening the mask so that it slopes into the undercut cavity and, thereafter, dry etching the bottom of the cavity.